Three dimensional vertical NAND strings are disclosed in an article by T. Endoh, et. al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36. However, this NAND string provides only one bit per cell. Furthermore, the active regions of the NAND string are formed by a relatively difficult and time consuming process involving repeated formation of memory openings and etching of a portion of the substrate, which results in a large diameter memory opening. Use of a substrate having a relatively high electrical resistance as the source line can result in reduced cell read current, variable resistance based on the location of the memory opening, and increased source line noise.